AlD CONVERTER WITH DIGITAL BACKGROUND CALIBRATION

This paper describes a 14-bit 2OMSPS switched-capacitor Stage Stae21t Sage N pipelined ADC that employs digital background calibration to N correct capacitor mismatch. The calibration concept is amenable to Digital correction Logic l_ Y implementation in SOC because it is digital in nature. The Digitalout calibration concept is demonstrated offline though in principle it can be included on-chip. The calibration can also be perfonned 2 periodically, thus is inherently able to track the operating VDAC conditions of the device. Implementation is in a complimentary bipolar process. The prototype exhibits typical INL of +/2.0 ts LSB, DNL of +/0.4 LSB, SNR of 73 dB and SFDR of 85 dB with a 2MHz input signal. Analog power is about 500mW with 5V Figure 1. A pipelined ADC. supply.